/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * i2c_const.h - I2C host driver code for LomboTech
 * i2c host driver macro define
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 */

#ifndef ___I2C___CONST__H___
#define ___I2C___CONST__H___

/******************************************************************************
 * feature
 *****************************************************************************/
#define I2C_TX_FIFO_DEPTH		16
#define I2C_RX_FIFO_DEPTH		16

/******************************************************************************
 * Control Register
 *****************************************************************************/
/*
 * speed mode (SPEED)
 */
#define I2C_SS_MODE			0
#define I2C_FS_MODE			1
#define I2C_HS_MODE			2


#define I2C_SS_SPK_LEN		4
#define I2C_FS_SPK_LEN		4
#define I2C_HS_SPK_LEN		2
#define I2C_HS_SPK_LEN_1	1

#define I2C_LCNT_MIN		6

/*
 * stop detect (STOP_DET)
 */
#define I2C_STOP_DET_IRR_MASTER_ACTIV	0
#define I2C_STOP_DET_IN_MASTER_ACTIV	1

/*
 * tx empty (TX_EMPTY)
 */
#define I2C_TX_EMPTY_AT_BELOW_TXTH	0
#define I2C_TX_EMPTY_IN_CMD_DONE	1

/******************************************************************************
 * Data Buffer and Command Register
 *****************************************************************************/
/*
 * transfer direction (CMD)
 */
#define I2C_CMD_WRITE			0
#define I2C_CMD_READ			1

/*
 * stop (STOP)
 */
#define I2C_NO_STOP			0
#define I2C_SEND_STOP			1

/*
 * restart (RESTART)
 */
#define I2C_NO_RESTART			0
#define I2C_SEND_RESTART		1

/******************************************************************************
 * Target Address Register
 *****************************************************************************/
/*
 * target address format (MASTER_10BITADDR)
 */
#define I2C_TAR_ADDR_7BIT		0
#define I2C_TAR_ADDR_10BIT		1

/******************************************************************************
 * STATUS Register
 *****************************************************************************/
#define I2C_STATUS_SDA_STK_NR			(1UL << 28)

#define I2C_STATUS_HOLD_RFF			(1UL << 25)
#define I2C_STATUS_HOLD_TFE			(1UL << 24)

#define I2C_STATUS_TX_DMA_REQ			(1UL << 19)
#define I2C_STATUS_TX_DMA_SINGLE		(1UL << 18)
#define I2C_STATUS_RX_DMA_REQ			(1UL << 17)
#define I2C_STATUS_RX_DMA_SINGLE		(1UL << 16)

#define I2C_STATUS_I2C_BUS_STATUS		(((1UL << 3) - 1) << 8)

#define I2C_STATUS_SDEV_F			(1UL << 6)
#define I2C_STATUS_ARAR_F			(1UL << 5)
#define I2C_STATUS_FSM_STATUS			(((1UL << 5) - 1) << 0)

/******************************************************************************
 * FIFO status Register
 *****************************************************************************/
#define I2C_STATUS_RX_EMPTY			(1UL << 17)
#define I2C_STATUS_TX_FULL			(1UL << 16)

#define I2C_STATUS_RX_FL			(((1UL << 5) - 1) << 8)
#define I2C_STATUS_TX_FL			(((1UL << 5) - 1) << 0)



/******************************************************************************
 * interrupt  (Interrupt Enable/Pending/Clear Register)
 *****************************************************************************/
#define I2C_INT_SCL_STK				(1UL << 21)
#define I2C_INT_SDA_STK				(1UL << 20)

#define I2C_INT_STOP_DET			(1UL << 18)
#define I2C_INT_RESTART_DET			(1UL << 17)
#define I2C_INT_START_DET			(1UL << 16)

#define I2C_INT_RX_FULL				(1UL << 13)
#define I2C_INT_TX_EMPTY			(1UL << 12)
#define I2C_INT_RX_OVER				(1UL << 11)
#define I2C_INT_RX_UNDER			(1UL << 10)
#define I2C_INT_TX_OVER				(1UL << 9)
#define I2C_INT_TX_UNDER			(1UL << 8)

#define I2C_INT_HLW				(1UL << 3)
#define I2C_INT_TX_ABRT				(1UL << 2)
#define I2C_INT_AUTO_FINISH			(1UL << 1)
#define I2C_INT_ACTIVITY			(1UL << 0)

#define I2C_INT_ALL_MASK			(0xFFFFFFFF)

#define I2C_INT_ALL_ERR		(I2C_INT_TX_ABRT | I2C_INT_TX_OVER | \
				I2C_INT_RX_OVER | I2C_INT_RX_UNDER)

/******************************************************************************
 * Transmit Abort Source Register
 *****************************************************************************/
#define I2C_ABT_DEVID_WRITE			(1UL << 20)
#define I2C_ABT_DEVID_ADDR_NAK			(1UL << 19)
#define I2C_ABT_DEVID_NAK			(1UL << 18)
#define I2C_ABT_SDA_SAL				(1UL << 17)

#define I2C_ABT_USER_ABRT			(1UL << 16)
#define I2C_ABT_MST_ARB_LOST			(1UL << 15)

#define I2C_ABT_SB_ACK				(1UL << 11)
#define I2C_ABT_HS_ACK				(1UL << 10)
#define I2C_ABT_GCALL_READ			(1UL << 9)
#define I2C_ABT_GCALL_NAK			(1UL << 8)

#define I2C_ABT_TD_NAK				(1UL << 4)
#define I2C_ABT_RA_NAK				(1UL << 3)
#define I2C_ABT_10A2_NAK			(1UL << 2)
#define I2C_ABT_10A1_NAK			(1UL << 1)
#define I2C_ABT_7A_NAK				(1UL << 0)

#define I2C_TX_ABTSRC_ALL_MASK			(0xFFFFFFFF)

#ifdef CONFIG_ARCH_LOMBO_N7V5
/* cqi status */
#define I2C_CQI_STATUS_BUSY			(1UL << 23)
#define I2C_CQI_STATUS_RS_DONE			(1UL << 31)


/* cqi int en/pd/cl */
#define I2C_CQI_INT_ERR			(1UL << 24)
#define I2C_CQI_INT_AF				(1UL << 31)
#define I2C_CQI_INT_SF				(1UL << 30)

#define I2C_CQI_ALL_INT		(I2C_CQI_INT_ERR | \
					I2C_CQI_INT_AF | I2C_CQI_INT_SF)

enum {
	REG_DATA_CMD,
	REG_INT_PD,
	REG_LEN,
	REG_TX_ABT_SOURCE,
	REG_INT_CLR,
	REG_CTL,
	REG_DAR,
	REG_ENABLE,
};

#endif

#endif /* ___I2C___CONST__H___ */
